This invention relates to digital dividers, and more particularly to X.5 divide circuits.
Digital circuits often employ dividers. For example, a clock operating at a higher frequency may be divided by a dividing circuit to generate a lower-frequency clock. Clocked flip-flops can be used when the divisor is a power of two, such as with divide-by-2N circuits, wherein N is a positive integer.
Sometimes a divisor is required that is not a power of two, or not even an integer. For example, a 333 MHz clock may be needed, but only a 500 MHz clock is available. The divisor needed is 500/333, or 1.5 (one and a half). Or a 200 MHz clock is needed, requiring a divider circuit with a divisor of 500/200=2.5, another non-integer divisor.
A variety of such divide by X.5 circuits have been developed, where X is a positive integer (whole number). The duty cycle produced by these circuits may not always be ideal. Sometimes the output clock's duty cycle is altered, such as when a 60%-40% or worse duty cycle is generated.
What is desired is a divide by X.5 circuit, wherein X is a whole number. A divide by X.5 circuit is desirable that has a near 50%—50% duty cycle.